代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/390483/8463428
bak mul16.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul16 is
port(clk:in std_logic;
a:in std_logic_vector(15 downto 0);
b:i
www.eeworm.com/read/390455/8464811
vhd xianshi.vhd
--XIANSHI
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XIANSHI IS
PORT( CLK0 : IN STD_LOGIC;
SEC_L,SEC_H,MIN_L,MIN_H : IN STD_LOGIC_VECTOR(6 DOWN
www.eeworm.com/read/390455/8464815
vhd dcnt6.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCNT6 IS
PORT(CLK:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
ENA: IN STD_LOGIC;
DATAIN:IN STD
www.eeworm.com/read/390455/8464821
vhd dcnt10.vhd
--DCNT10.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCNT10 IS
PORT(CLK:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
ENA: IN STD_LOGIC;
www.eeworm.com/read/390455/8464824
vhd jsq.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY JSQ IS PORT(
COOK : IN STD_LOGIC;
DATA3 : IN STD_LOGIC_VECTOR(15 DOWNTO 0
www.eeworm.com/read/189192/8485959
vhd ldenaddsub.vhd
--
-- This is an adder-subtractor VHDL module.
-- The module is a parallel loadable, synchronous
-- set/reset, clock enabled adder-subtractor.
-- this code implements a simple and compact
-- add
www.eeworm.com/read/390020/8489058
vhd clk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk is
port(
clk : in std_logic;
address : out std_logic_vector(5 downto 0));
end clk;
a
www.eeworm.com/read/290095/8505614
vhd fulladder_4.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FullAdder_4 IS
PORT(dataA,dataB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carryin:IN STD_LOGIC;
sum:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carryout:OUT S
www.eeworm.com/read/290081/8506943
vhd clkdiv_2p5.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ClkDiv_2p5 IS
PORT(clk:IN STD_LOGIC;
clkdiv2p5:OUT STD_LOGIC);
END ENTITY ClkD
www.eeworm.com/read/389644/8509644
txt 数控分频器的设计.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PULSE IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FO