代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/411221/11251458
vhd reg_8rst.vhd
-- "reg_8rst.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gene
www.eeworm.com/read/411221/11251462
vhd reg_pc.vhd
-- "reg_pc.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Genera
www.eeworm.com/read/411221/11251486
vhd reg_s.vhd
-- "reg_s.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General
www.eeworm.com/read/411221/11251489
vhd reg_8t.vhd
-- "reg_8t.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Genera
www.eeworm.com/read/411212/11251928
vhd count_6.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count_6 IS
PORT(clk,clr: IN STD_LOGIC;
co:OUT STD_LOGIC;
qout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
www.eeworm.com/read/411212/11252061
vhd count_10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count_10 IS
PORT(clk,clr: IN STD_LOGIC;
co:OUT STD_LOGIC;
qout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0
www.eeworm.com/read/411211/11252492
vhd multi8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY multi8 IS
PORT(
clk,start:IN STD_LOGIC;--乘法启动信号，高电平复位与加载，低电平运算
a,b :IN STD_LOGIC_V
www.eeworm.com/read/249841/12466815
vhd iface.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library
www.eeworm.com/read/249838/12467293
cmp ddr_sdram.cmp
-- Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS
www.eeworm.com/read/336141/12474947
vhd ctl_1.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Entity ctl_1 is
Port(
wr :in std_logic; -- 作时钟使用
A :in std_logic_vector(15 downto 0); -- 16位地址线
D :in std_logic_vector(7 downto 0); --