代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
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vhd min4_e.vhd
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---- ----
---- min4_e.vhd
www.eeworm.com/read/173695/9641488
vhd trellis1_e.vhd
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---- ----
---- trellis1_e.vhd
www.eeworm.com/read/173672/9643807
vhd divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
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vhd dataclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity dataclk is
port(
clk:in std_logic;
reset:i
www.eeworm.com/read/369385/9651784
vhd ex88.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ex88 IS
PORT
(
in1,in2 : STD_LOGIC_vector;
pout : OUT STD_LOGIC_vector
);
END ex88;
ARCHITECTURE a OF ex88 IS
BEGIN
PR
www.eeworm.com/read/369385/9652113
vhd dataclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity dataclk is
port(
clk:in std_logic;
reset:i
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vhd division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
www.eeworm.com/read/369317/9655033
vhd usbcomm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -
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vhd led.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LED is
port(
A : in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
WR : in STD_LOGIC; -- 写使能
DWR : in STD_LOGIC_VECTOR(
www.eeworm.com/read/172723/9695538
txt dct8_slow.txt
-- Top entity is DCT8_slow
-- ENTITY DCT8_slow IS
-- PORT(
-- clk : IN std_logic ;
-- dctselect : IN std_logic ;
-- din : IN std_logic ;
--