led.vhd

fpga usb接口系统设计实例,实现了usb通讯

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LED is
	port(
		A :   in  STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
		WR :  in  STD_LOGIC;                     -- 写使能
		DWR : in  STD_LOGIC_VECTOR(7 downto 0);  -- 数据总线
		LED : out STD_LOGIC_VECTOR(6 downto 0)   -- LED段码
		);
end xspLED;
architecture BHV of LED is
begin	
	process(A, DWR, WR)
	begin
		if A(15 downto 12)= "1111" then
			if rising_edge(WR) then
				LED<= DWR(6 downto 0);
			end if;
		end if;
	end process;
end BHV;