代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/252132/12300415
vhd flipflop.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
www.eeworm.com/read/252132/12300441
vhd regne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( n : INTEGER := 4 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN
www.eeworm.com/read/252132/12300443
vhd latch.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT ( D, clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END latch ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PR
www.eeworm.com/read/252132/12300481
vhd regne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( n : INTEGER := 4 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN
www.eeworm.com/read/252132/12300492
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
COMPONENT addern -- n-bit adder
GENERIC ( n : INTEGER := 4 ) ;
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LO
www.eeworm.com/read/252132/12300494
vhd components.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
COMPONENT addern -- n-bit adder
GENERIC ( n : INTEGER := 4 ) ;
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LO
www.eeworm.com/read/252132/12300498
vhd serial.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY serial IS
GENERIC ( length : INTEGER := 8 ) ;
PORT ( Clock : IN STD_LOGIC ;
Reset : IN STD_LOGIC ;
A, B : IN STD_LOGIC_VECT
www.eeworm.com/read/252132/12300499
vhd shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
www.eeworm.com/read/252132/12300511
vhd shiftrne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
-- left-to-right shift register with parallel load and enable
ENTITY shiftrne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTO
www.eeworm.com/read/252132/12300561
vhd regne.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regne IS
GENERIC ( N : INTEGER := 4 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn : IN STD_LOGIC ;
E, Clock : IN