latch.vhd

一本很好的关于学习VHDL的书,Fundamentals of Digital Logic with VHDL Design,我的导师在教我VHDL时使用的教材.上传的是书内包含的所有的代码.

LIBRARY ieee ; 
USE ieee.std_logic_1164.all ; 

ENTITY latch IS 
	PORT ( 	D, clk 	: IN 	STD_LOGIC ; 
			Q 		: OUT 	STD_LOGIC ) ; 
END latch ;

ARCHITECTURE Behavior OF latch IS    
BEGIN
	PROCESS ( D, clk ) 
	BEGIN
		IF clk = '1' THEN 
			Q <= D ; 
		END IF ; 
	END PROCESS ; 
END Behavior ;