代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/339072/12262659
cmp nco.cmp
-- Generated by NCO 2.2.0 [Altera, IP Toolbench v1.2.5 build28]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- *******
www.eeworm.com/read/338599/12292630
vhd command.vhd
--#############################################################################
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Altera
www.eeworm.com/read/252132/12300187
vhd latch.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT ( D, Clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END latch ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PRO
www.eeworm.com/read/252132/12300200
vhd shift.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY lpm ;
USE lpm.lpm_components.all ;
ENTITY shift IS
PORT ( Clock : IN STD_LOGIC ;
Reset : IN STD_LOGIC ;
Shiftin, Load :
www.eeworm.com/read/252132/12300244
vhd subccts.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE subccts IS
COMPONENT regn
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_L
www.eeworm.com/read/252132/12300252
vhd proc.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
USE work.subccts.all ;
ENTITY proc IS
PORT ( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Reset, w : IN STD_
www.eeworm.com/read/252132/12300260
vhd subccts.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE subccts IS
COMPONENT regn
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_L
www.eeworm.com/read/252132/12300300
vhd shiftn.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shiftn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Clock : IN STD_LOGIC ;
L, w : IN S
www.eeworm.com/read/252132/12300312
vhd implied.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY implied IS
PORT ( A, B : IN STD_LOGIC ;
AeqB : OUT STD_LOGIC ) ;
END implied ;
ARCHITECTURE Behavior OF implied IS
BEGIN
PROCE
www.eeworm.com/read/252132/12300343
vhd implied.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY implied IS
PORT ( A, B : IN STD_LOGIC ;
AeqB : OUT STD_LOGIC ) ;
END implied ;
ARCHITECTURE Behavior OF implied IS
BEGIN
PROCE