implied.vhd

一本很好的关于学习VHDL的书,Fundamentals of Digital Logic with VHDL Design,我的导师在教我VHDL时使用的教材.上传的是书内包含的所有的代码.

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY implied IS
	PORT ( 	A, B 	: IN 	STD_LOGIC ;
			AeqB	: OUT 	STD_LOGIC ) ;
END implied ;

ARCHITECTURE Behavior OF implied IS	
BEGIN
	PROCESS ( A, B )
	BEGIN
		IF A = B THEN
			AeqB <= '1' ;
		END IF ;
	END PROCESS ;
END Behavior ;