代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
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vhd reg.vhd

-- Register set -- size:(size) a generic -- -- clk--posedge clock input -- rst--asynchronous reset -- pst--asynchronous preset -- load--active high input loads register -- d--register input --
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vhd topcon.vhd

--############################################################################### -- -- LOGIC CORE: SDR SDRAM Controller -- MODULE NAME: Controller() -- da
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vhd controller.vhd

--############################################################################### -- -- LOGIC CORE: SDR SDRAM Controller -- MODULE NAME: Controller() -
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vhd command.vhd

--############################################################################# -- -- LOGIC CORE: Command module -- MODULE NAME: command() -- COMPANY: Altera Cor
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vhd cnt24.vhd

LIBRARY IEEE; -- 24进制计数器 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT24 IS PORT ( CLK,EN, U_D : IN STD_LOGIC;
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vhd dds_vhdl.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DDS_VHDL IS -- 顶层设计 PORT ( CLK : IN STD_LOGIC; CLK_DA
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vhd dds.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DDS IS -- 顶层设计 PORT ( CLK : IN STD_LOGIC; DA_CLK : OUT
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vhd etester.vhd

LIBRARY IEEE; -- 2004;GWDVPB 选择模式5 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY etester IS PORT (BCLK : IN STD_LOGIC; --标准频率时钟信号CLOCK2:P124 TCLK : IN STD_L
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vhd test.vhd

LIBRARY IEEE; -- 2002/2/1 GWDVPB USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY etester IS PORT (BCLK : IN STD_LOGIC; --标准频率时钟信号 TCLK : IN STD_LOGIC; --PI
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vhd ball.vhd

--乒乓球灯模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ball is port(clk:in std_logic;--乒乓球灯前进时钟 clr:in std_logic;--乒乓球灯清零 way:in std_logic;--乒乓球灯前进方向 en