topcon.vhd

sdram控制器

--###############################################################################
--
--  LOGIC CORE:          SDR SDRAM Controller 							
--  MODULE NAME:         Controller()                	
--  date:		 2006.8.19
--  REVISION HISTORY:  
--  FUNCTIONAL DESCRIPTION:
--
--  This module is the state_machine for the SDR SDRAM controller.
--  Copyright (C) 1991-2000 
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity topcon1 is
       port (
               	clk            	: in      std_logic;                            --!系统时钟由 pll产生，100mhz                 	               	
		clkop          	: out      std_logic;
	        reset          	: in      std_logic;
		pllreset        : in      std_logic;
		fifo1rden       : out     std_logic;			       --fifo的使能信号高电平有效
	        fifo2wren       : out     std_logic;
		hostdataen      : out     std_logic;	        
		HostAdr         : in      std_logic_vector(22 downto 0);	--???外部提供的随机地址信号
		HostDataout     : out     std_logic_vector(15 downto 0);	--随机读写数据
		HostDatain      : IN      std_logic_vector(15 downto 0);	--随机读写数据		
		DataWr		: in	  std_logic_vector(15 downto 0);	--!give to add_mode外部输入数据，可连接前端fifo，或选通后接主机数据总线
		DataRd		: out     std_logic_vector(15 downto 0);	--外部输出数据，可连接后端fifo，或选通后接主机数据总线
		reqack       	: out 	  std_logic;
		PageWeAdrSet    : in 	  std_logic;		                --!页写首地址复位信号
		PageRdAdrSet    : in 	  std_logic;                           	--!页读首地址复位信号          	
		FIFO1AlmostF    : IN 	  std_logic;
		FIFO2AlmostE    : IN 	  std_logic;
		TransferMode 	: IN 	  std_logic;
		HostWr 		: IN 	  std_logic;
		HostRd 		: IN 	  std_logic;		
		LOCK		: out 	  std_logic;
		CLKOS		: out 	  std_logic;					       
		SA              : out     std_logic_vector(11 downto 0);        --???SDRAM address output
         	BA              : out     std_logic_vector(1 downto 0);         --SDRAM bank address
		CS_N            : out     std_logic;                		--SDRAM Chip Selects
         	CKE             : out     std_logic;                            --SDRAM clock enable
         	RAS_N           : out     std_logic;                            --SDRAM Row address Strobe
         	CAS_N           : out     std_logic;                            --SDRAM Column address Strobe
         	WE_N            : out     std_logic;                            --SDRAM write enable
         	DQ              : inout   std_logic_vector(15 downto 0);        --！SDRAM data bus
         	DQM             : out     std_logic_vector(1 downto 0) ;  	--SDRAM data mask lines
------------------------------test use-----------------------------------
--		operationreqt : 	out std_logic_vector(2 downto 0);
--		cmdt       	: out     std_logic_vector(2 downto 0);         --输出当前的状态
--		count1         	: out 	  std_logic_vector(2 downto 0);
--		sdramint        : out     std_logic_vector(15 downto 0);	--接口输入数据总线；
--		sdramoutt   	: out     std_logic_vector(15 downto 0);	--接口输出数据总线
		CMDACKtt	: out     std_logic
--		cmdlengthcount	: out     std_logic_vector(9 downto 0);
--		tcmdlengthcount : out      std_logic_vector(9 downto 0)
);
end topcon1;

architecture operation of topcon1 is
			
	 signal operationreqi :  std_logic_vector(2 downto 0):="000";  
	 signal clkouti       :  std_logic;
	 signal cmdstate      :  std_logic_vector(3 downto 0):="0000";
	 
	 signal reqacki       :  std_logic:='0';
	
	signal CLKOPi       :  std_logic;
---------------------------------------------------------
	signal sdramint         :  std_logic_vector(15 downto 0);
	signal sdramoutt        :  std_logic_vector(15 downto 0);

	signal cmdlengthcount	:  std_logic_vector(9 downto 0);
	signal	tcmdlengthcount :  std_logic_vector(9 downto 0);
	signal cmdt       	:  std_logic_vector(2 downto 0);
	signal count1         	:  std_logic_vector(2 downto 0);
	signal operationreqt 	:  std_logic_vector(2 downto 0);
	COMPONENT l 
    	port (
        CLK: in std_logic; 
        RESET: in std_logic; 
        CLKOP: out std_logic; 
        CLKOS: out std_logic; 
        LOCK: out std_logic);
	end COMPONENT;

	COMPONENT controller
	PORT(
		clk 		: IN std_logic;
		clkout		: out std_logic;
		operationreq	: IN std_logic_vector(2 downto 0);
		reset 		: IN std_logic;
		cmdstate 	: out     std_logic_vector(3 downto 0);         --输出当前的状态
	       	cmdt       	: out     std_logic_vector(2 downto 0);         --输出当前的状态
		CMDACKt		: out     std_logic;
		cmdlengthcount	: out     std_logic_vector(9 downto 0);	
		HostAdr 	: IN std_logic_vector(22 downto 0); --??
		DataWr		: IN std_logic_vector(15 downto 0);
		PageWeAdrSet 	: IN std_logic;
		PageRdAdrSet 	: IN std_logic;
		reqack 		: out     std_logic; 
		HostDataout	: OUT std_logic_vector(15 downto 0);
		HostDatain 	: IN std_logic_vector(15 downto 0);
		DQ 		: INOUT std_logic_vector(15 downto 0);      
		HostRd 		: IN std_logic;
		sdramin          : out      std_logic_vector(15 downto 0);	--接口输入数据总线；
		sdramout   	: out     std_logic_vector(15 downto 0);	--接口输出数据总线	
		count1         : out std_logic_vector(2 downto 0);
		fifo1rden : 	out      std_logic;			       --fifo的使能信号高电平有效
	        fifo2wren : 	out      std_logic;
		hostdataen: 	out      std_logic;
		DataRd : 	OUT std_logic_vector(15 downto 0);
		
		SA : 		OUT std_logic_vector(11 downto 0);
		BA : 		OUT std_logic_vector(1 downto 0);
		CS_N : 		OUT std_logic;
		CKE : 		OUT std_logic;
		RAS_N : 	OUT std_logic;
		CAS_N : 	OUT std_logic;
		WE_N : 		OUT std_logic;
		DQM : 		OUT std_logic_vector(1 downto 0);
--------------------------------------------------------------------------
		tcmdlengthcount : out      std_logic_vector(9 downto 0)
		);
	END COMPONENT;

	COMPONENT Arbitrate
	PORT(
		SdramClk 	: 	IN std_logic;
		ResetGlb 	: 	IN std_logic;
		FIFO1AlmostF 	: 	IN std_logic;
		FIFO2AlmostE 	: 	IN std_logic;
		HostWr 		: 	IN std_logic;
		HostRd 		: 	IN std_logic;
		TransferMode 	: 	IN std_logic;
		OperationAck 	: 	IN std_logic;          
		OperationReq 	: 	OUT std_logic_vector(2 downto 0)
		
		);
	END COMPONENT;
	
	begin
	clkop <= CLKOPi;
	operationreqt <=operationreqi;
	reqack<= reqacki;
	Arb: Arbitrate PORT MAP(
		
		SdramClk 	=> CLKOPi,				--!
		ResetGlb 	=> reset,				--!
		FIFO1AlmostF 	=> FIFO1AlmostF,			--!
		FIFO2AlmostE 	=> FIFO2AlmostE,			--!
		HostWr 		=> HostWr,				--!
		HostRd 		=> HostRd,				--!
		TransferMode 	=> TransferMode,			--!
		OperationAck 	=> reqacki,			--!
		OperationReq 	=> operationreqi			--!
		
	);

	
	clock: l 
    	port MAP(
        CLK	=> clk,	 
        RESET	=> pllreset, 
        CLKOS	=> CLKOPi, 
        CLKOP	=> CLKOS, 
        LOCK	=> LOCK);
	
	
	con: controller PORT MAP(
	  
		clk 		=> CLKOPi,					
		clkout 		=> clkouti,				--!
		operationreq 	=> operationreqi,			--!
		cmdstate 	=> cmdstate,				--!
		cmdt       	=> cmdt,        --输出当前的状态
		CMDACKt		=> CMDACKtt, 
		cmdlengthcount 	=> cmdlengthcount,		--!
		reset 		=> reset,					--!
		reqack 		=> reqacki,				--!
	 	fifo1rden 	=> fifo1rden,			       --!fifo的使能信号高电平有效
	 	fifo2wren	=> fifo2wren,			--!
	 	hostdataen	=> hostdataen,			--!
		HostAdr 	=> HostAdr,				--!
		HostDataout 	=> HostDataout,			--!
		HostDatain 	=> HostDatain,			--!
		DataWr 		=> DataWr,				--!
		DataRd 		=> DataRd,				--!
		PageWeAdrSet 	=> PageWeAdrSet,			--!
		PageRdAdrSet 	=> PageRdAdrSet,			--!
		HostRd 		=> HostRd,
		sdramin         => sdramint,	--接口输入数据总线；
		sdramout   	=> sdramoutt,	--接口输出数据总线
		count1         => count1,
		SA 		=> SA,					--!
		BA 		=> BA,					--!
		CS_N 		=> CS_N,					--!
		CKE 		=> CKE,					--!
		RAS_N 		=> RAS_N,
		CAS_N 		=> CAS_N,
		WE_N 		=> WE_N,
		DQ 		=> DQ,
		DQM 		=> DQM,					--!
----------------------------------------------------------------
		tcmdlengthcount 	=> tcmdlengthcount	
	);
	
end operation;