代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
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vhd mc8051_rom_.vhd

------------------------------------------------------------------------------- -- -- -- X X XXXXXX XXXXXX
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vhd reg.vhd

-- reg.vhd -- This module implements a 16-bit general purpose register. The contents of -- register is loaded on the rising edge of "clk". It is cleared to zero when -- "reset" is asserted low. T
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vhd pc.vhd

-- pc.vhd -- This module implements the 16-bit program Counter (PC). PC is loaded from -- PCIn on the next clock when "PCControl" is asserted high. PC is cleared to -- zero when "reset" is assert
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txt 加法器源程序 .txt

------------------------------------------------------------------------ -- Single-bit adder ------------------------------------------------------------------------ library IEEE; use IEEE.std_log
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txt 相应加法器的测试向量(test bench).txt

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------
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txt 加法器描述.txt

-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------------------------------ -- Single-bit adder -----------------------
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txt eclock.txt

library ieee; use ieee.std_logic_1164.all; package my_pkg is component div1024 port(clk: in std_logic; f1hz: out std_logic); end component; component count60 port(carry: in std_logic;
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vhd avr_core.vhd

--************************************************************************************************ -- Top entity for AVR core -- Version 1.11 -- Designed by Ruslan Lepetenok -- Modified 03.11.200
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vhd ramdatareg.vhd

--********************************************************************************************** -- RAM data register for the AVR Core -- Version 0.1 -- Modified 02.11.2002 -- Designed by Ruslan Lepe
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vhd counter10.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter10 is Port ( clk : in std_logic; reset : in std_logic; din : in std_logic_vector