代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/478253/6722879
vhd bsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto
www.eeworm.com/read/477858/6724017
txt dds.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT (clk :IN STD_LOGIC;
K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
RESET:IN S
www.eeworm.com/read/477872/6725095
txt dds.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT (clk :IN STD_LOGIC;
K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
RESET:IN S
www.eeworm.com/read/477679/6730847
vhd lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --3.125MHZ FROM div16 Module
www.eeworm.com/read/477743/6733676
vhdl blowfishsbox.vhdl
-- Copyright © 2007 Wesley J. Landaker
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis
www.eeworm.com/read/477206/6740145
vhd 4xuan1.vhd
LIBRARY IEEE;
USE IEEE. STD_LOGIC_1164.ALL;
ENTITY sixuanyi IS
PORT(i0:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
i1:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
i2:IN STD_LOGIC_VECTOR (7 DOWNTO
www.eeworm.com/read/477377/6742341
vhdl testbenchri.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity instr_reg_test is
end entity;
architecture arch of instr_reg_test is
signal done : boolean := fa
www.eeworm.com/read/477377/6742370
vhdl bancregistre.vhdl
LIBRARY ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reg_file is
port( clk: in std_logic;
www.eeworm.com/read/477377/6742374
vhdl testbenchregflag.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity status_reg_test is
end entity;
architecture arch of status_reg_test is
signal done : boolean := false;
signal p
www.eeworm.com/read/477377/6742378
bak testbenchri.vhdl.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity instr_reg_test is
end entity;
architecture arch of instr_reg_test is
signal done : boolean := false;
signal pass