代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
www.eeworm.com/read/493461/6393843

vhd cell13.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:06:49 04/22/08 -- Design Name: -- Module Name: cell13 -
www.eeworm.com/read/493461/6393855

vhd cell3.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:06:49 04/22/08 -- Design Name: -- Module Name: cell3 -
www.eeworm.com/read/493461/6393860

vhd cell11.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:06:49 04/22/08 -- Design Name: -- Module Name: cell11 -
www.eeworm.com/read/493461/6393861

vhd cell10.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:06:49 04/22/08 -- Design Name: -- Module Name: cell10 -
www.eeworm.com/read/493461/6393886

vhd cell17.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:06:49 04/22/08 -- Design Name: -- Module Name: cell17 -
www.eeworm.com/read/493461/6393892

vhd cell1.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:06:49 04/22/08 -- Design Name: -- Module Name: cell1 -
www.eeworm.com/read/493461/6393893

vhd cell4.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:06:49 04/22/08 -- Design Name: -- Module Name: cell4 -
www.eeworm.com/read/492919/6413923

txt 4位微处理器系统的顶层描述.txt

4位微处理器系统的顶层描述。 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; USE IEEE.NUMERIC_STD.ALL ; PACKAGE cpu4_comps IS COMPONENT alumux PORT( D,Q,A,B:IN UNSI
www.eeworm.com/read/491205/6441721

vhd txmittest.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity txmittest is port( tx:out std_logic; txclkout:out std_logic;--For test send clok; data:in std_logic_vecto
www.eeworm.com/read/491206/6441780

vhd division10.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity division10 is port(lin:in std_logic_vector(9 downto 0); clock:in std_logic;