4位微处理器系统的顶层描述.txt

4位微处理器系统的顶层描述代码

4位微处理器系统的顶层描述。

LIBRARY  IEEE ;
USE  IEEE.STD_LOGIC_1164.ALL ;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE  IEEE.NUMERIC_STD.ALL ;
PACKAGE  cpu4_comps  IS
COMPONENT  alumux
  PORT(  D,Q,A,B:IN UNSIGNED(3 DOWNTO 0);
         ALUIN_CTRL : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
         R,S : BUFFER UNSIGNED(3 DOWNTO 0) );
END COMPONENT; 

COMPONENT alu  
  PORT( R,S : IN UNSIGNED(3 DOWNTO 0);
     ALU_CTRL: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
     CIN: IN STD_LOGIC;
     F:BUFFER UNSIGNED(3 DOWNTO 0);
     G_BAR,P_BAR: BUFFER STD_LOGIC;
     C4:BUFFER STD_LOGIC;
     OVR:BUFFER STD_LOGIC );
END COMPONENT; 

COMPONENT ram1  
  PORT( CLK: IN STD_LOGIC;
       Aaddr,Baddr,F: IN UNSIGNED(3 DOWNTO 0);
       RAM1_CTRL :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
       RAM0,RAM3:INOUT STD_LOGIC;
       A,B: BUFFER UNSIGNED (3 DOWNTO 0) );
END COMPONENT; 

COMPONENT qreg1 
  PORT ( CLK :  IN  STD_LOGIC ;
       F: IN UNSIGNED(3 DOWNTO 0) ;
       Q_CTRL :IN STD_LOGIC_VECTOR(2 DOWNTO 0) ;
       Q0,Q3:INOUT STD_LOGIC ;
       Q: BUFFER UNSIGNED (3 DOWNTO 0) ) ;
END COMPONENT; 

COMPONENT outmux  
  PORT( A, F :  IN UNSIGNED(3 DOWNTO 0);
       MUX_CTRL :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
       OE : IN STD_LOGIC;
       Y: BUFFER UNSIGNED (3 DOWNTO 0) );
END COMPONENT; 
END  cpu4_comps ;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.cpu4_comps.ALL;
ENTITY cpu4 IS
  PORT( CLK: IN STD_LOGIC;
       Aaddr,Baddr: IN UNSIGNED(3 DOWNTO 0);
       D:IN UNSIGNED(3 DOWNTO 0);
       I:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
       CIN : IN STD_LOGIC;
        OE: IN STD_LOGIC;
        RAM0,RAM3:INOUT STD_LOGIC;
        Q0,Q3:INOUT STD_LOGIC; 
        Y: BUFFER UNSIGNED (3 DOWNTO 0);
        G_BAR,P_BAR:BUFFER STD_LOGIC;
        C4:  BUFFER STD_LOGIC;
         OVR: BUFFER STD_LOGIC;
         F_0:  BUFFER STD_LOGIC;
         F_3:BUFFER STD_LOGIC ) ;
END  ENTITY  cpu4 ;

ARCHITECTURE  arc1  OF 	cpu4  IS
     SIGNAL ALUIN_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(2 DOWNTO 0);
     SIGNAL ALU_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(5 DOWNTO 3);
     SIGNAL RAM1_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(8 DOWNTO 6);
     SIGNAL Q_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(8 DOWNTO 6);
     SIGNAL MUX_CTRL: STD_LOGIC_VECTOR(2 DOWNTO 0):= I(8 DOWNTO 6);
     SIGNAL A,B: UNSIGNED(3 DOWNTO 0);
     SIGNAL Q: UNSIGNED(3 DOWNTO 0);
     SIGNAL R,S: UNSIGNED(3 DOWNTO 0);
     SIGNAL F: UNSIGNED(3 DOWNTO 0);
  BEGIN
     U1: ram1   PORT MAP (CLK,Aaddr,Baddr,F,RAM1_CTRL,RAM0,RAM3,A,B) ;
     U2: qreg1  PORT MAP (CLK,F,Q_CTRL,Q0,Q3,Q) ;
     U3: alumux  PORT MAP (D,Q,A,B,ALUIN_CTRL,R,S) ;
     U4: alu   PORT MAP ( R,S,ALU_CTRL,CIN,F,G_BAR,P_BAR,C4,OVR) ;
     U5: outmux  PORT MAP ( A,F,MUX_CTRL,OE,Y) ;
    F_3 <=  F(3) ;
    F_0 <=  '0'  WHEN  F = "0000" ;
END  ARCHITECTURE  arc1 ;