代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/311947/13620940
vhd miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to th
www.eeworm.com/read/311947/13620942
vhd txunit.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to th
www.eeworm.com/read/310977/13638754
vhd dff9.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff9 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
Dout : OUT STD_LOGIC_V
www.eeworm.com/read/310741/13644705
vhd my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
www.eeworm.com/read/310741/13644708
vhd shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
www.eeworm.com/read/310741/13644730
vhd divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
www.eeworm.com/read/310741/13644745
vhd shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s
www.eeworm.com/read/310677/13647158
vhd uc_interface.vhd
-- File: uC_interface.vhd
--
-- Author: Jennifer Jenkins
-- Philips Semiconductor
-- Purpose: Description of an interface with a ucontroller/uprocessor
-- (i.e. Motorola 68000)
www.eeworm.com/read/309919/13661941
vhd txmit_tb.vhd
-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v
www.eeworm.com/read/309833/13663876
vhd receive_top.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:17:58 12/01/2007
-- Design Name:
-- Module Name: rece