代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/325597/13194957
vhd my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
www.eeworm.com/read/325597/13194966
vhd shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
www.eeworm.com/read/325597/13195039
vhd divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
www.eeworm.com/read/325597/13195091
vhd shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s
www.eeworm.com/read/138839/13208532
vhd bintobcd2.vhd
----串行输入（高位在前）的二进制数转换成十进制（BCD码），在n个时钟脉冲下转化n个二这十进制数
----这是4 bits 二进制数转化成十进制(BCD码)的模块，可以级连使用，转化更多的二进制数
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_log
www.eeworm.com/read/138605/13228516
vhd my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
www.eeworm.com/read/138605/13228526
vhd shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
www.eeworm.com/read/138605/13228591
vhd divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
www.eeworm.com/read/138605/13228630
vhd shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s
www.eeworm.com/read/240240/13229721
vhd fftoutbuf.vhd
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--
use IEEE.math_real.all;
use IEEE.math_complex.all;
library work;
use work.fftDef.all;
--
use work.fftDataType.all;