代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
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txt adder_vhd.txt
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
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txt testadder_vhd.txt
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
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vhd chapter10_models.vhd
entity DECIMATE is
generic (DEC: INTEGER);
port ( RX,IX: in REAL:=0.0;
N: in REAL:=0.0;
RY,IY: out REAL:=0.0;);
end DECIMATE;
architecture BEHAVIOR of DECIMATE is
begin
proce
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vhd cnt24.vhd
LIBRARY IEEE; -- 24进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT24 IS
PORT ( CLK,EN, U_D : IN STD_LOGIC;
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vhd and2.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity and2 is
port (
c: out STD_LOGIC;
a: in STD_LOGIC;
b: in STD_LOGIC
);
end and2;
architecture and2_arch of
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keyscan66noreset
-- KEY BOARD
-------------------------------------
--000 *A* *B* *C* *D* *E* *F*
--001 *G* *H* *I* *J* *K* *L*
--010 *M* *N* *O* *P* *Q* *R*
--011 *S
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vhd my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
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vhd shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
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vhd divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
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vhd shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s