代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/145129/12752317
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/145059/12754578
vhd 加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/145059/12754580
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/145059/12754621
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/246102/12756159
vhd touch.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity touch is
port (
reset : in std_logic;
c
www.eeworm.com/read/246102/12756175
cmp pci.cmp
-- Generated by PCI Compiler 4.1.1 [Altera, IP Toolbench v1.2.11 build48]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
www.eeworm.com/read/332405/12759633
vhd ihdlutil.vhd
--
-- interHDL proprietary information
-- Copyright (C) 1990-1998 interHDL inc.
-- All rights reserved.
--
-- ihdlutil package. produced by interVHDL (R)
-- ihdlutil package. Implements utility functi
www.eeworm.com/read/144784/12772528
txt newclock.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity newclock is
port(clk :in std_logic;
segout :out std_logic_vector(7 downt
www.eeworm.com/read/144784/12772531
txt newclock.vhd.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity newclock is
port(clk :in std_logic;
segout :out std_logic_vector(7 downt
www.eeworm.com/read/332097/12780880
vhd interfazv1.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity interfaz is
port (
clk: in STD_LOGIC;
resetz: in STD_LOGIC;
data: in STD_LOGIC_VECTOR(5 downto 0);
habili