touch.vhd

div的verilog开发程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity touch is 
         port (
              reset  : in std_logic;
              clk    : in std_logic;
              q      : out std_logic;
              div    : out std_logic_vector(3 downto 0)
              );
end touch;

architecture rtl of touch is
 
 signal a :  std_logic_vector(3 downto 0);
 signal c :  std_logic;

begin 
process(clk,reset)
begin
 if reset = '0' then
   a<="0000"; 
  elsif clk'event and clk = '1' then 
     if (a = "1111") then 
        a<=(others=>'0');
        q<= '0';
     else
         a<=a+1;
        q<= '1';
     end if ;
  end if;

end process;

   div <= a ;


end rtl;