代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/196115/8114492
vhd memoryremapper.vhd
--****************************************************************************************************
-- Memory remapper for ARM core simualtion
-- Designed by Ruslan Lepetenok
-- Modified 26.12.2
www.eeworm.com/read/196115/8114535
vhd abusmultiplexer.vhd
--****************************************************************************************************
-- A bus multiplexer for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.1
www.eeworm.com/read/196115/8114566
vhd msscomppackage.vhd
-- *****************************************************************************************
-- Components for ARM memory subsystem (simulation)
-- Designed by Ruslan Lepetenok
-- Modified 02.02.20
www.eeworm.com/read/196115/8114592
vhd mulctrlandregs.vhd
--****************************************************************************************************
-- Multiplier control and Partial Sum/Carry registers for ARM core
-- Designed by Ruslan Lepete
www.eeworm.com/read/196115/8114610
vhd multipliertestadder.vhd
--****************************************************************************************************
-- Adder for multiplier tester for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 27.01.
www.eeworm.com/read/196115/8114622
vhd arm7tdmis_top.vhd
--****************************************************************************************************
-- Top entity for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 05.02.2003
www.eeworm.com/read/196115/8114641
vhd multiplier.vhd
--****************************************************************************************************
-- Multiplier for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 07.12.2002
--*********
www.eeworm.com/read/195920/8122374
vhd dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC;
CLK_DA
www.eeworm.com/read/195913/8123802
vhd ball.vhd
--乒乓球灯模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball is
port(clk:in std_logic;--乒乓球灯前进时钟
clr:in std_logic;--乒乓球灯清零
way:in std_logic;--乒乓球灯前进方向
en
www.eeworm.com/read/295958/8131342
vhd hdb3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3 is
port(reset,clk,codein: in std_logic;
codeout: out std_logic_vector(1 downto 0));
end;
ar