代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/298078/7975555
vhd cnt45.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT45 IS
PORT( CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
S4:OUT STD_LOGIC;
LOAD:IN BIT;
Q4
www.eeworm.com/read/297990/7981830
vhd bl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bl is
PORT(
C:in std_logic_vector(2 downto 0);
opcode:in std_logic_vector(7 downto 0);
downto0: in
www.eeworm.com/read/297990/7982185
vhd car.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity car is
port(
cin: in std_logic_vector(7 downto 0);
add1,load,reset,clk: in std_logic;
www.eeworm.com/read/197597/7984750
vhd 加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/197597/7984754
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/197597/7984810
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/398041/8008502
vhd select_32.vhd
library ieee;
use ieee.std_logic_1164.all;
entity select_32 is
port( A:in std_logic_vector(15 downto 0);
B:in std_logic_vector(15 downto 0);
S:in std_logic;
Y:out std_logic_vector(15
www.eeworm.com/read/398041/8008519
bak select_32.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
entity select_32 is
port( A:in std_logic_vector(15 downto 0);
B:in std_logic_vector(15 downto 0);
S:in std_logic;
Y:out std_logic_vector(15
www.eeworm.com/read/297535/8012260
vhd timec.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY timec IS
PORT( seca: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
secb: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
mina: IN STD
www.eeworm.com/read/297458/8016565
cmp ddr_sdram.cmp
-- Generated by DDR SDRAM Controller 6.1 [Altera, IP Toolbench v1.3.0 build70]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE