bl.vhd

用VHDL编的简易CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bl is
	PORT(
		 C:in std_logic_vector(2 downto 0);
		 opcode:in std_logic_vector(7 downto 0);
		 downto0: in std_logic;
		 mpyshift: in std_logic;
		 mpyadd: in std_logic;
		 mpysub: in std_logic;
		 flag : in std_logic_vector(1 downto 0);
		 accdownto0: in std_logic;
		 address: buffer std_logic_vector(7 downto 0);
		 add1car,loadcar,resetcar: out std_logic
		 );
end bl;

architecture a of bl is
begin
	process
	  begin
		 if(c(0)='1')then
		  add1car<='1';
		  loadcar<='0';
		  resetcar<='0';
		 elsif(c(1)='1')then
          add1car<='0';
		  loadcar<='1';
		  resetcar<='0';
		 elsif(c(2)='1')then
	 	  add1car<='0';
		  loadcar<='0';
		  resetcar<='1';
		 end if;
	end process;

	address<="00010000" when opcode="00010000" else --load
		"00100000" when opcode="00100000" else --store
		"00110000" when opcode="00110000" else --add
		"01000000" when opcode="01000000" else --sub
		"01010000" when opcode="01010000" else --halt
		"01100000" when opcode="01100000" else--and
		"01110000" when opcode="01110000" else--or
		"10000000" when opcode="10000000" else--not
		"10010000" when opcode="10010000" else--shiftr
		"10100000" when opcode="10100000" else--shiftl
		"10110000" when opcode="10110000" and downto0='0' and flag(0)='0'and flag(1)='0' else 			--mpy
		"11000000" when opcode="10110000" and flag(1)='1' and downto0='0' and mpyshift='1' else 		--mpyshift	
		"11010000" when opcode="10110000" and flag(1)='1' and downto0='0' and mpysub='1' else 			--mpysub
		"11100000" when opcode="10110000" and flag(1)='1' and downto0='0' and mpyadd='1' else 			--mpyadd
		"10110110" when opcode="10110000" and flag(0)='1' else  						--go back
		"10110111" when opcode="10110000" and downto0='1' and flag(1)='1' else			--end
		"11110000" when opcode="11110000" and accdownto0='1'else 				--jmpgez
		"11110010" when opcode="11110000" and accdownto0='0'else		
		"00000000";
	end a;