代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/460301/7254015
vhd sdram_tb.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use WORK.common.all;
use WORK.rand.all;
use WORK.mem.all;
use WORK.sdram.all;
ENTITY sdram
www.eeworm.com/read/460301/7254018
vhd sdramcntl.vhd
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
package sdram is
-- SDRAM controller
component sdramCntl
generic(
FREQ : natural := 50_000; -- operating fr
www.eeworm.com/read/460295/7254096
vhd songer.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT
(CLK1MHZ :IN STD_LOGIC; --主频1M
CAIDENG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --彩灯功能
PP : IN STD_LOGI
www.eeworm.com/read/460213/7255344
vhd txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto
www.eeworm.com/read/460213/7255418
vhd xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
www.eeworm.com/read/460213/7255446
vhd xor32.vhd
--xor32
library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
use Ieee.std_logic_arith.all;
entity xor32 is
port(h1,h2,m1,m2,h3,h4,m3,m4:in std_logic_vector(3 downto 0);
www.eeworm.com/read/460213/7255614
vhd division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
www.eeworm.com/read/460213/7255645
vhd bsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto
www.eeworm.com/read/459461/7275185
vhd interfazv1.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity interfaz is
port (
clk: in STD_LOGIC;
resetz: in STD_LOGIC;
data: in STD_LOGIC_VECTOR(5 downto 0);
habili
www.eeworm.com/read/458110/7304971
vhd counter16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter16 is
port(
clr: in std_logic;
fin: IN std_logic;
start: in std_logic;
Q