counter16.vhd

来自「利用VHDL编写的一个简单的16位计数器」· VHDL 代码 · 共 29 行

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity counter16 is    
port( 
  clr: in std_logic;    
  fin: IN std_logic;     
  start: in std_logic;     
  Q: OUT std_logic_vector(15 downto 0) 
  ); 
end;  

architecture behav of counter16 is    
signal Qtemp:std_logic_vector(15 downto 0); 
begin 
process(clr,fin,start) 
begin 
  if clr='1' then Qtemp<=(others=>'0'); 
  elsif fin'event and fin='1' then 
   if start='1' then 
    Qtemp<=Qtemp+1; 
   end if; 
   end if;
Qtemp<=Qtemp; 

end process; 
Q<=Qtemp; 
end behav;