代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/267307/6933500
vhd sram_r.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_R IS
PORT(
DATASIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DATAMOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO
www.eeworm.com/read/429250/6943411
vhd vga.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package vga_pckg is
component vga
generic (
FREQ : natural := 50_000; -- master clock frequency (in KHz)
CLK_DIV
www.eeworm.com/read/385303/6946575
vhd songer.vhd
LIBRARY IEEE; -- 硬件演奏电路顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT ( CLK4 : IN STD_LOGIC; --音调频率信号
CLK6 :
www.eeworm.com/read/385303/6946674
bak songer.vhd.bak
LIBRARY IEEE; -- 硬件演奏电路顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS
PORT ( CLK1 : IN STD_LOGIC; --音调频率信号
CLK2 :
www.eeworm.com/read/320898/6960959
vhd divfsm.vhd
----------------------------------------------------
--
-- VHDL code generated by Visual HDL
--
-- Design Unit:
-- ------------
-- Unit Name : DIV_FSM_CU
-- Library Name
www.eeworm.com/read/468520/6992163
bak demux74155.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux74155 is
port(din: in std_logic;
s: in std_logic_vector(1 downto 0);
y: out st
www.eeworm.com/read/468520/6992171
vhd demux74155.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux74155 is
port(din: in std_logic;
s: in std_logic_vector(1 downto 0);
y: out st
www.eeworm.com/read/467491/7004346
vhd division.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity division is
generic(SIZE: INTEGER := 8);
port(reset: in STD_LOGI
www.eeworm.com/read/466968/7025606
vhd efcount.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity efcount is
port (bclk :in std_logic;-- standard clock
tclk :in std_logic;-- measured clock
c
www.eeworm.com/read/466968/7025676
bak efcount.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity efcount is
port (bclk :in std_logic;-- standard clock
tclk :in std_logic;-- measured clock
c