divfsm.vhd

X8086的VHDL源码

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--  
--      VHDL code generated by Visual HDL
--
--  Design Unit:
--  ------------
--      Unit    Name  :  DIV_FSM_CU
--      Library Name  :  my_eu
--  
--      Creation Date :  Wed Feb 06 00:38:59 2002
--      Version       :  6.7.0.patch1-pc build 20 from Feb 20 2001
--  
--  Options Used:
--  -------------
--      Target
--         HDL        :  VHDL
--         Purpose    :  Synthesis
--         Vendor     :  Synplify
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  1 File per Unit
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         IF for state selection         :  No
--         Preserve spacing for free text :  Yes
--         Sort Ports by mode             :  No
--         Declaration alignment          :  No
--
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----------------------------------------------------
--  
--  Library Name :  my_eu
--  Unit    Name :  DIV_FSM_CU
--  Unit    Type :  State Machine
--  
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library ieee;
use ieee.std_logic_1164.all;
use work.UPAC.ALL;

entity DIVFSM is
	port( I_CLK      :  in std_logic;
		  I_RST      :  in std_logic;
	      I_BW       :  in std_logic;
          I_DIV      :  in std_logic;
		  I_LOOPEND  :  in std_logic;
          I_NEGA     :  in std_logic;
          O_DIVSTATE : out std_logic_vector( 3 downto 0 )
          ); 
end DIVFSM;
  
architecture RTL of DIVFSM is
  
constant INITIAL  : std_logic_vector( 3 downto 0 ) := "0000";
constant AX_LD    : std_logic_vector( 3 downto 0 ) := "0011";
constant DATA_LD  : std_logic_vector( 3 downto 0 ) := "0001";
constant DX_LD    : std_logic_vector( 3 downto 0 ) := "0010";
constant MOD_ST   : std_logic_vector( 3 downto 0 ) := "1000";
constant Q_SET    : std_logic_vector( 3 downto 0 ) := "0111";
constant Q_ST     : std_logic_vector( 3 downto 0 ) := "1001";
constant SHIFT_L  : std_logic_vector( 3 downto 0 ) := "0101";
constant SIGN_SET : std_logic_vector( 3 downto 0 ) := "1010";
constant SUB      : std_logic_vector( 3 downto 0 ) := "0110";
constant ZERO_SET : std_logic_vector( 3 downto 0 ) := "0100";

signal   divstate     : std_logic_vector( 3 downto 0 );
signal   currentstate : std_logic_vector( 3 downto 0 );
  
begin

	O_DIVSTATE <= currentstate;

	process(I_CLK,I_RST,divstate)
	begin
		if (I_RST = RST_ACT ) then
			currentstate <= INITIAL;
		elsif (I_CLK'event and I_CLK = '0') then
			currentstate <= divstate;
		end if;
	end process;

	DIV_FSM_CU_initial:
	process(currentstate,I_DIV,I_BW,I_LOOPEND,I_NEGA)
	begin
		case currentstate is
		when INITIAL =>
			if (I_DIV = '1') then
				divstate <= DATA_LD;
			else
				divstate <= INITIAL;
			end if;
		when AX_LD =>
			divstate <= ZERO_SET;
		when DATA_LD =>
			if    (I_BW = '0') then
				divstate <= AX_LD;
			else
				divstate <= DX_LD;
			end if;
		when DX_LD =>
			divstate <= AX_LD;
		when MOD_ST =>
			divstate <= Q_ST;
		when Q_SET =>
			if (I_LOOPEND = '1') then
				if (I_NEGA = '1') then
					divstate <= SIGN_SET;
				else
					divstate <= MOD_ST;
				end if;
			else
				divstate <= SHIFT_L;
			end if;
		when Q_ST =>
			divstate <= INITIAL;
		when SHIFT_L =>
			divstate <= SUB;
		when SIGN_SET =>
			divstate <= MOD_ST;
		when SUB =>
			divstate <= Q_SET;
		when ZERO_SET =>
			divstate <= SHIFT_L;
		when others =>
			divstate <= INITIAL;
		end case;
	end process;
 
end RTL;