代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/416057/11043086
vhd multipliertestadder.vhd
--****************************************************************************************************
-- Adder for multiplier tester for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 27.01.
www.eeworm.com/read/416057/11043092
vhd arm7tdmis_top.vhd
--****************************************************************************************************
-- Top entity for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
www.eeworm.com/read/416057/11043101
vhd multiplier.vhd
--****************************************************************************************************
-- Multiplier for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
--*********
www.eeworm.com/read/267307/6933144
vhd sram_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_1 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
www.eeworm.com/read/267307/6933190
vhd sram_2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_2 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
www.eeworm.com/read/267307/6933195
vhd sram_rslow.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_R IS
PORT(
DATASIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DATAMOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO
www.eeworm.com/read/267307/6933390
vhd sram_r.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_R IS
PORT(
DATASIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DATAMOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO
www.eeworm.com/read/267307/6933437
vhd sram_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_1 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
www.eeworm.com/read/267307/6933477
vhd sram_2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_2 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
www.eeworm.com/read/267307/6933482
vhd sram_rslow.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SRAM_R IS
PORT(
DATASIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DATAMOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO