代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/164962/10080410
txt adder_variety_style.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/164942/10081155
vhd my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
www.eeworm.com/read/164942/10081158
vhd shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
www.eeworm.com/read/164942/10081184
vhd divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
www.eeworm.com/read/164942/10081202
vhd shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s
www.eeworm.com/read/360684/10082125
vhd uc_interface.vhd
-- File: uC_interface.vhd
--
-- Author: Jennifer Jenkins
-- Philips Semiconductor
-- Purpose: Description of an interface with a ucontroller/uprocessor
-- (i.e. Motorola 68000)
www.eeworm.com/read/360253/10105504
cmp viterbi_ber.cmp
-- Generated by Viterbi Compiler 4.1.0 [Altera, IP Toolbench v1.2.5 build28]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE
www.eeworm.com/read/164155/10125844
vhd control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(q:in std_logic_vector(1 downto 0);
codeout:in std_logic;
am,fout:in std_logic_vecto
www.eeworm.com/read/164154/10127421
vhd count1024.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count1024 is
port(clk:in std_logic;
c1024:out std_logic);
end;
architecture one of count1024 is
si
www.eeworm.com/read/164131/10128060
vhd bsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto