control.vhd

dds信号发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(q:in std_logic_vector(1 downto 0);
      codeout:in std_logic;
      am,fout:in std_logic_vector(7 downto 0);
      dout:out std_logic_vector(7 downto 0));
end;
architecture one of control is
begin
process(q,codeout)
begin
if q="00" then dout<=fout;
elsif q="01" then dout<=am;
elsif q="10" and codeout='1' then dout<=fout;
elsif q="10" and codeout='0' then dout<="10000000";
else dout<=fout;
end if;
end process;
end;