代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
www.eeworm.com/read/165425/10062833

vhdl usb_new_usbvpb_top_str.vhdl

-------------------------------------------------------------------------------- -- -- P H I L I P S C O M P A N Y R E S T R I C T E D -- -- Copyright
www.eeworm.com/read/165425/10062886

vhdl usb_new_usbpvci_ent.vhdl

-------------------------------------------------------------------------------- -- -- P H I L I P S C O M P A N Y R E S T R I C T E D -- -- Copyright
www.eeworm.com/read/361154/10065830

vhd xspcore.vhd

-------------------------------------------------------------------------------- -- Copyright (c) 2000 by Trenz Electronic. -- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de --
www.eeworm.com/read/361154/10065836

vhd xspuc.vhd

-------------------------------------------------------------------------------- -- Copyright (c) 2000 by Trenz Electronic. -- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de --
www.eeworm.com/read/361154/10065846

vhd xspusb.vhd

-------------------------------------------------------------------------------- -- Copyright (c) 2000 by Trenz Electronic. -- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de --
www.eeworm.com/read/165328/10067373

vhd mydesign.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_1164.aLL; ENTITY mydesign IS PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK,EOC:IN STD_LOGIC; CLK1:IN STD_LOGIC
www.eeworm.com/read/361043/10068049

vhd pilchard.vhd

library ieee; use ieee.std_logic_1164.all; entity pilchard is port ( PADS_exchecker_reset: in std_logic; PADS_dimm_ck: in std_logic; PADS_dimm_cke: in std_logic_vector(1 downto 0); PADS_dimm_ras:
www.eeworm.com/read/360965/10070888

cmp fft.cmp

-- Generated by FFT 7.1 [Altera, IP Toolbench 1.3.0 Build 177] -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- ********
www.eeworm.com/read/164962/10080355

vhd testadder.vhd

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------
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vhd adder.vhd

------------------------------------------------------------------------ -- Single-bit adder ------------------------------------------------------------------------ library IEEE; use IEEE.std_log