mydesign.vhd

请先删除编译后的debug/release目录以减少压缩包大小

LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.aLL;
ENTITY mydesign  IS
  PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       CLK,EOC:IN STD_LOGIC;
          CLK1:IN STD_LOGIC;
          ADDA,OE,STA,ALE:OUT STD_LOGIC;
          DOUT: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
           y:OUT STD_LOGIC;
             Q:BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0));
END SZDYB;
ARCHITECTURE  CHENZHIJUN  OF  mydesign IS
SIGNAL Y9:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL Y8:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL Y7:STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT ADC
  PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       EOC,CLK:IN STD_LOGIC;
       ADDA,OE,STA,ALE:OUT STD_LOGIC;
       Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT ADC0809;
COMPONENT shuaifa1
  PORT(din:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      qq:OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
END COMPONENT shuaifa1;
COMPONENT XZQ31
  PORT(INPUT:IN STD_LOGIC_VECTOR(11 DOWNTO 0);
         SES:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
           Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT XZQ31;
COMPONENT WX
  PORT(CLK:IN STD_LOGIC;   Y:OUT STD_LOGIC;
         Q:BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT WX;
COMPONENT deled7
  PORT(INPUT: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        DOUT: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT deled7;        BEGIN
  U1:ADC PORT MAP(D,EOC,CLK,ADDA,OE,STA,ALE,Y9);
  U2:shuaifa1  PORT MAP(Y9,Y8);
  U3:XZQ31   PORT MAP(Y8,Q,Y7);
  U4:WX      PORT MAP(CLK1,y,Q);
  U5:deled7  PORT MAP(Y7,DOUT);
END  CHENZHIJUN;