代码搜索:std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/189192/8485975
vhd comparator.vhd
------
-- VHDL module for a comparator
-- this module contains two implementations for the
-- comparsion. Not all synthesis tools will accept
-- both implementations. However, these two impleme
www.eeworm.com/read/433102/8545979
vhd counter.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter IS
PORT(
CLKB:IN STD_LOGIC;--标准频率信号
TCLK:IN STD_LOGIC;--待测频率信号
CLR:IN STD_LOGIC;
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vhd change.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity change is
port
( period,clk:in std_logic;
n1,n2,n3:in std_logic_vector(3 downto 0);
m1,m2,m3:in std_logi
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vhd counter10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
port(clk:in std_logic;
reset:in std_logic;
di
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vhd counter24.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter24 is
port(clk:in std_logic;
reset:in std_logic;
www.eeworm.com/read/433021/8551542
vhd ps2.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity PS2 is
port ( KBdata: in STD_LOGIC;
KBCLK: in STD_LOGIC;
DOUT: out STD_LOGIC_VEC
www.eeworm.com/read/433021/8551880
vhd 与非门_hct00.vhd
--Quad 2-input Nand
--Simple concurrent model of a TTL quad nand gate.
--uses 1993 std VHDL
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT00 is
port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logi
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vhd 加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
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vhd count_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins