代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/229456/14338400
cmp lpm_rom1.cmp
--Copyright (C) 1991-2005 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any outpu
www.eeworm.com/read/229368/14343336
txt abc.txt
2.4.1CPLD 与单片机双向串行通信原理
单片机到CPLD的串行通信接口电路是利用VHDL语言在CPLD中设计一
个串行输入并行输出的八位移位寄存器，其端口与单片机P1.4~P1.7 相连。如
图2-12 所示。CS 为单片机片选信号，当其为低时使能八位寄存器；当CPLD
发出READEY 信号有效CLK1 信号的上升沿到达DCLK 端口时，八位移位寄
存器就会将单片机输出到ram ...
www.eeworm.com/read/228966/14356743
vhd xspfpga.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
www.eeworm.com/read/228367/14388221
vhd cntm100v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm100v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in
www.eeworm.com/read/228367/14388251
vhd cntm24v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm24v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in s
www.eeworm.com/read/228367/14388428
vhd cntm60v.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--------------------
ENTITY cntm60v IS
PORT(en: IN std_logic;
clr:in std_logic;
clk:in
www.eeworm.com/read/228099/14400723
vhd service_module.vhd
--**********************************************************************************************
-- Some additional control registers for the AVR Core
-- Version 0.7 20.05.2003
-- Designed by Ru
www.eeworm.com/read/228099/14400733
vhd io_reg_file.vhd
--************************************************************************************************
-- Internal I/O registers (implemented inside the core) decoder/multiplexer
-- for AVR core
-- Ve
www.eeworm.com/read/228098/14400773
vhd regfile.vhd
--****************************************************************************************************
-- Register file for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 23.01.2003
--******
www.eeworm.com/read/228098/14400806
vhd alu.vhd
--****************************************************************************************************
-- ALU for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 16.12.2002
--****************