代码搜索：shift

找到约 10,000 项符合「shift」的源代码

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srs cmd_shift.srs

# # # # Created by Synplify VHDL Compiler version Compilers 7.3, Build 073R from Synplicity, Inc. # Copyright 1994-1999 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Fri
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fse ctr_shift.fse

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srs ctr_shift.srs

# # # # Created by Synplify VHDL Compiler version Compilers 7.3, Build 073R from Synplicity, Inc. # Copyright 1994-1999 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Sun
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srm ctr_shift.srm

@E"VRMNFMl;C"RHyVDjCR "VRob:\ssFoNVlRH#DC\M#$bODHH\0$#b$MD$HV_\(dD\HLP\E8#308P"E8;VRyHRDC4R V"\o:l8$_Co#HM[#\00C#\N[0o#j\sOO\0#s_E0HV38PE"y;RVCHDRV. R:"o\FbsolsNRDVHC##\$DMbH0OH$$\#MHbDV($_dH\DLE\P
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ncf ctr_shift.ncf

# # Constraints generated by Synplify Pro 7.3, Build 170R # # Period Constraints #Begin clock constraints #End clock constraints # Output Constraints # Input Constraints # Location Con
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srs cmd_shift_in.srs

# # # # Created by Synplify VHDL Compiler version Compilers 7.3, Build 073R from Synplicity, Inc. # Copyright 1994-1999 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Sat
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txt shift register.txt

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primi
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c bn_shift.c

/* crypto/bn/bn_shift.c */ /* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) * All rights reserved. * * This package is an SSL implementation written * by Eric Young (eay@cryptsoft.com).
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vhd shift_reg.vhd

library ieee; use ieee.std_logic_1164.all; entity shift_reg is generic( dlzka : natural :=7); port( datain : in std_logic; clk : in std_logic; rst : in std_logic; ss : in std_logic;
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m sig_shift.m

function [yshift,n]=sig_shift(x,m,n0) %信号延迟的程序，m为输入x的下标 %n0为延迟的单位长度 n=m+n0; yshift=x; function [yam,n]=sig_proc(x1,n1,x2,n2,s) %信号相加和相乘的程序 %x1，x2分别为输入序列，n1，n2为对应下标 %s=0为加法；其他值为乘法 n=min(min(
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