代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/18104/775076
jhd shift_register_tb.jhd
MODULE shift_register_tb
SUBMODULE shift_register
www.eeworm.com/read/18114/775247
v adi_shift_revd.v
`timescale 1 ps / 1ps
module ADI_Shift_RevD (
data_in,
rxclk_p,
rxclk_n,
fco_en_p,
fco_en_n,
par_data_a,
par_data_b,
par_data_c,
par_data_d,
fco_latch
);
input [3:0] data_i
www.eeworm.com/read/18141/776372
bsf shift_r1.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/18141/776937
v shift_r1.v
/**************************************************
函数名：shift_r1
功 能：实现数据的串行输入并行输出
参数说明：clk 时钟
flag 标志信号，当完整接收到一个回答信号后则由此发出一个脉冲
data_in 输入的数据
dat
www.eeworm.com/read/18159/777752
vhd shift_register_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : Test Bench for shift_register
-- Design : UART
-- Author : Xinghua
www.eeworm.com/read/18163/778473
xco shift_reg2.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\work\ISE\c11
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/18163/778561
xco rake_shift4.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c12
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/18288/783285
vhd shift_register_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : Test Bench for shift_register
-- Design : UART
-- Author : Xinghua
www.eeworm.com/read/18288/783300
jhd shift_register_tb.jhd
MODULE shift_register_tb
SUBMODULE shift_register
www.eeworm.com/read/18360/785785
vhd shift_register_tb.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : Test Bench for shift_register
-- Design : UART
-- Author : Xinghua