代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/18089/774769
v adi_shift.v
`timescale 1 ps / 1ps
module ADI_Shift (
data_in,
otr8,
rxclk_p,
rxclk_n,
fco_en_p,
fco_en_n,
par_data_o,
par_data_a,
par_data_b,
par_data_c,
par_data_d,
fco_latch
);
i
www.eeworm.com/read/18104/775082
vhd shift_register.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity shift_register is
-- 类属参数
generic (
TOTAL_BIT : integer := 10 );
-- 端口
port (
clk : in std_logic;
reset_n : in std_lo
www.eeworm.com/read/18141/776370
bsf shift_reg.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/18141/776939
v shift_reg.v
/**************************************************
函数名：shift_reg
功 能：实现数据的并行输入串行输出
参数说明：clk 时钟
busy 忙信号，1时忙不能写入数值
0时可以写入新的数值
data_in 输入的数据
www.eeworm.com/read/18141/776947
vwf shift_reg.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/18159/777769
vhd shift_register.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity shift_register is
-- 类属参数
generic (
TOTAL_BIT : integer := 10 );
-- 端口
port (
clk : in std_logic;
reset_n : in std_lo
www.eeworm.com/read/18163/778494
xco shift16.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c11
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysym
www.eeworm.com/read/18164/778580
vhd ram_shift.vhd
-- PARALLE IN PARALLEL OUT SHIFTER IN THE ADDRESS GENERATION UNIT.
-- REQUIRED BECAUSE FFT IS COMPUTED ON DATA AND WRITTEN BACK INTO THE SAME
-- LOCATION AFTER 5 CYCLES. SO THE READ ADDRESS IS SHIFT
www.eeworm.com/read/18164/778592
vhd shift2.vhd
-- SHIFT UNIT
library ieee ;
use ieee.std_logic_1164.all ;
use work.butter_lib.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
entity shift2 is
port (
sub_contr