代码搜索:shift

找到约 10,000 项符合「shift」的源代码

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www.eeworm.com/read/231684/14223678

vhd shift2.vhd

-- SHIFT UNIT library ieee ; use ieee.std_logic_1164.all ; use work.butter_lib.all ; use ieee.std_logic_arith.all ; use ieee.std_logic_unsigned.all ; entity shift2 is port ( sub_contr
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vhd shift1.vhd

---- ---- ---- This file is part of the G711 a-law project ---- ---- http://www.opencores.org/cores/G711/ ---- ---- Description: ITU-T G.711 a-law codec, asynchronous shifter module ---- Implementatio
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vhd ram_shift.vhd

-- PARALLE IN PARALLEL OUT SHIFTER IN THE ADDRESS GENERATION UNIT. -- REQUIRED BECAUSE FFT IS COMPUTED ON DATA AND WRITTEN BACK INTO THE SAME -- LOCATION AFTER 5 CYCLES. SO THE READ ADDRESS IS SHIFT
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vhd shift2.vhd

-- SHIFT UNIT library ieee ; use ieee.std_logic_1164.all ; use work.butter_lib.all ; use ieee.std_logic_arith.all ; use ieee.std_logic_unsigned.all ; entity shift2 is port ( sub_contr
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rpt shift.asm.rpt

Assembler report for shift Tue Dec 27 17:38:08 2005 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2.
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rpt shift.fit.rpt

Fitter report for shift Tue Dec 27 17:38:06 2005 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Fi
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summary shift.map.summary

Flow Status : Successful - Tue Dec 27 17:38:04 2005 Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version Revision Name : shift Top-level Entity Name : shift Family : MAX3000A Device : EP
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rpt shift.map.rpt

Analysis & Synthesis report for shift Tue Dec 27 17:38:04 2005 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal N
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eqn shift.map.eqn

--B1_T_CLK is shiftout:inst|T_CLK B1_T_CLK_p0_out = !reset & !B1_rdy & !B1_T_CLK & B1_bitcount[0]; B1_T_CLK_p1_out = !reset & B1_rdy & B1_T_CLK; B1_T_CLK_p2_out = !reset & !B1_rdy & !B1_T_CLK & B1_
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eqn shift.fit.eqn

--B1_T_CLK is shiftout:inst|T_CLK at LC3 B1_T_CLK_p0_out = !reset & !B1_rdy & !B1_T_CLK & B1_bitcount[0]; B1_T_CLK_p1_out = !reset & B1_rdy & B1_T_CLK; B1_T_CLK_p2_out = !reset & !B1_rdy & !B1_T_CL