shift1.vhd

g711-pcm的音频编码ＶＨＤＬ源代码

---- ----
---- This file is part of the G711 a-law project ----
---- http://www.opencores.org/cores/G711/ ----
---- Description: ITU-T G.711 a-law codec, asynchronous shifter module
---- Implementation of G711 a-law IP core according to ----
---- G711 a-law IP core specification document. ----
---- Author(s): Tokarev Victor 
---- e-mail:  [e-mail] ----
---- ----
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---- ----
---- Copyright (C) 2002 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
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LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY shift1 IS
	PORT
	(
		distance		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		data		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
	);
END shift1;

ARCHITECTURE SYN OF shift1 IS
BEGIN
	with distance select 
		result <=data when "000",
	 			 data (10 downto 0)& data(11)  when "001",
				 data (9 downto 0)& data(11 downto 10) when "010",
				 data (8 downto 0)& data(11 downto 9) when "011",
				 data (7 downto 0)& data(11 downto 8) when "100",
		 		 data (6 downto 0)& data(11 downto 7) when "101",
				 data (5 downto 0)& data(11 downto 6) when "110",
				 data (4 downto 0)& data(11 downto 5) when others;

END SYN;