shift.vhd

来自「g711-pcm的音频编码ＶＨＤＬ源代码」· VHDL 代码 · 共 63 行

---- ----
---- This file is part of the G711 a-law project ----
---- http://www.opencores.org/cores/G711/ ----
---- Description: ITU-T G.711 a-law codec, asynchronous shifter module
---- Implementation of G711 a-law IP core according to ----
---- G711 a-law IP core specification document. ----
---- Author(s): Tokarev Victor 
---- e-mail:  [e-mail] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2002 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY shift IS
	PORT
	(
		distance		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		data		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
	);
END shift;

ARCHITECTURE SYN OF shift IS
BEGIN
	with distance select 
		result <=data (4 downto 0) when "000",
	 			 data (5 downto 1) when "001",
				 data (6 downto 2) when "010",
				 data (7 downto 3) when "011",
				 data (8 downto 4) when "100",
		 		 data (9 downto 5) when "101",
				 data (10 downto 6) when "110",
				 '1' & data(10 downto 7) when others;

END SYN;