代码搜索：sequential
找到约 1,846 项符合「sequential」的源代码
代码结果 1,846
www.eeworm.com/read/281827/4112431
f90 trl_comm_none.f90
! $Id: trl_comm_none.f90,v 1.1 2004/05/04 06:29:35 fowlkes Exp $
!!!
! All communication routines used by TRLAN are in this file.
! This file contains routines to be used on sequential or shared memor
www.eeworm.com/read/430506/1929486
m smoker.m
% SMOKER Sequential Minimal Optimization for SVM (L1).
% [Alpha,bias,nsv,trn_err,margin]=smoker(K,labels,C,eps,tol,Alpha,bias)
%
% SMOKER is the SMO which uses precomputed kernel matrix
% insted of
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m som_seqtrain.m
function [sMap, sTrain] = som_seqtrain(sMap, D, varargin)
%SOM_SEQTRAIN Use sequential algorithm to train the Self-Organizing Map.
%
% [sM,sT] = som_seqtrain(sM, D, [[argID,] value, ...])
%
% sM
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m smoker.m
% SMOKER Sequential Minimal Optimization for SVM (L1).
% [Alpha,bias,nsv,trn_err,margin]=smoker(K,labels,C,eps,tol,Alpha,bias)
%
% SMOKER is the SMO which uses precomputed kernel matrix
% insted of
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f90 flush_1.f90
! { dg-do run }
! PR 22390 Implement flush statement
program flush_1
character(len=256) msg
integer ios
open (unit=10, access='SEQUENTIAL', status='SCRATCH')
write (10, *) 42
flush 1
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f90 write_check3.f90
! { dg-do run }
! PR29936 Missed constraint on RECL=specifier in unformatted sequential WRITE
! Submitted by Jerry DeLisle
program us_recl
real, dimension(5) :: array = 5.43
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m som_seqtrain.m
function [sMap, sTrain] = som_seqtrain(sMap, D, varargin)
%SOM_SEQTRAIN Use sequential algorithm to train the Self-Organizing Map.
%
% [sM,sT] = som_seqtrain(sM, D, [[argID,] value, ...])
%
% sM
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m som_seqtrain.m
function [sMap, sTrain] = som_seqtrain(sMap, D, varargin)
%SOM_SEQTRAIN Use sequential algorithm to train the Self-Organizing Map.
%
% [sM,sT] = som_seqtrain(sM, D, [[argID,] value, ...])
%
% sM
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m smoker.m
% SMOKER Sequential Minimal Optimization for SVM (L1).
% [Alpha,bias,nsv,trn_err,margin]=smoker(K,labels,C,eps,tol,Alpha,bias)
%
% SMOKER is the SMO which uses precomputed kernel matrix
% insted of
www.eeworm.com/read/413190/11163698
vhd instruction_register.vhd
library ieee;
use ieee.std_logic_1164.all; -- each module will need to use std_logic
entity instruction_register is
port( reset : in std_logic; -- master reset, same for each sequential module