代码搜索：sequence
找到约 10,000 项符合「sequence」的源代码
代码结果 10,000
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rpt m_sequence.tan.rpt
Classic Timing Analyzer report for m_sequence
Mon Apr 20 01:01:41 2009
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
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; Table of Contents ;
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www.eeworm.com/read/469268/6979757
bak m_sequence.v.bak
module m_sequence(q,clock,reset);
output q;
input clock;
input reset;
reg q;
reg [31:0] PRBS;
integer i;
integer j;
always@(posedge clock)
begin
if(reset==1)
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smsg m_sequence.map.smsg
Warning (10268): Verilog HDL information at m_sequence.v(9): Always Construct contains both blocking and non-blocking assignments
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rpt m_sequence.fit.rpt
Fitter report for m_sequence
Mon Apr 20 01:01:27 2009
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
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; Table of Contents ;
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www.eeworm.com/read/469268/6979764
rpt m_sequence.asm.rpt
Assembler report for m_sequence
Mon Apr 20 01:01:37 2009
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
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; Table of Contents ;
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www.eeworm.com/read/469268/6979765
summary m_sequence.map.summary
Analysis & Synthesis Status : Successful - Mon Apr 20 01:01:16 2009
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
Revision Name : m_sequence
Top-level Entity Name : m_sequence
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rpt m_sequence.sim.rpt
Simulator report for m_sequence
Mon Apr 20 01:01:54 2009
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
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; Table of Contents ;
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www.eeworm.com/read/469268/6979768
rdb m_sequence.sim.rdb
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hier_info m_sequence.hier_info
|m_sequence
q q~reg0.CLK
reset => ~NO_FANOUT~
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qmsg m_sequence.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}