m_sequence.v.bak

一种m序列扩频接收机设计代码

module m_sequence(q,clock,reset);
   output q;
   input clock;
   input reset;
   reg q;
   reg [31:0] PRBS;
   integer i;
   integer j;
 always@(posedge clock)
  begin
   if(reset==1)
    begin
     for(i=0;i<32;i=i+1)
     PRBS[i]=1;
    end   
      for(j=0;j<31;j=j+1)
      PRBS[j+1]<=PRBS[j];
      PRBS[0]<=PRBS[31]^PRBS[30];
      q<=PRBS[0];
    end
    endmodule