代码搜索：second
找到约 10,000 项符合「second」的源代码
代码结果 10,000
www.eeworm.com/read/460213/7255510
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
entity second is
port(a,b,c,zin,yin:in std_logic;
dout,eout,fout,gout:out std_logic);
end second;
architecture rtl of second is
begin
www.eeworm.com/read/455332/7373233
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
www.eeworm.com/read/455332/7373244
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位
www.eeworm.com/read/452918/7429253
java second.java
import javax.swing.*;
import java.awt.*;
import java.awt.event.*;
public class second
{
public static void main(String[] args)
{
DemoSwingFrame frame = new DemoSwingFrame();
www.eeworm.com/read/452540/7437333
bsf second.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/452540/7437334
bdf second.bdf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/452228/7444223
qpf second.qpf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/452228/7444241
qsf second.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/452228/7444290
vhd second.vhd
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY second IS
PORT(
clk, reset,setsec : IN STD_LOGIC;
enmin : OUT STD_LOGIC;
daout: out std_logic_vector