代码搜索：optimize

找到约 6,026 项符合「optimize」的源代码

代码结果 6,026
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/372607/2771492

tdf scfifo_j4p.tdf

--scfifo DEVICE_FAMILY="Cyclone II" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=6 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" clock data empty ful
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www.eeworm.com/read/366702/2878050

c memcmp.c

extern void abort(void); extern int inside_main; int memcmp (const void *s1, const void *s2, __SIZE_TYPE__ len) { const unsigned char *sp1, *sp2; #ifdef __OPTIMIZE__ if (inside_main) abort (
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www.eeworm.com/read/361782/2943221

regkeys

CommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\cpldfit.exe -ise F:/MiniStep_v1.0/MiniStep.ise -intstyle ise -p xc9536-10-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs
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www.eeworm.com/read/361782/2943254

regkeys

CommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\cpldfit.exe -ise F:/MiniStep_v1.0/MiniStep.ise -intstyle ise -p xc9536-10-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs
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www.eeworm.com/read/361782/2943287

regkeys

CommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\cpldfit.exe -ise F:/xc95114/MiniStep/MiniStep.ise -intstyle ise -p xc9536-10-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inpu
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www.eeworm.com/read/154076/5643086

xcp dpram_core.xcp

# Xilinx CORE Generator 5.1i SELECT Dual_Port_Block_Memory Virtex2P Xilinx,_Inc. 4.0 CSET primitive_selection = Optimize_For_Area CSET port_a_active_clock_edge = Rising_Edge_Triggered CSET port_a_
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www.eeworm.com/read/471424/6892535

xcp buffer_img.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/471424/6892539

xcp tabla_q.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/471424/6892540

xcp buffer_comp_chrom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/471424/6892547

xcp q_rom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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