代码搜索：optimize

找到约 6,026 项符合「optimize」的源代码

代码结果 6,026
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/430383/8752107

xcp buffer_comp_chrom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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xcp q_rom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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xcp buffer_comp.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/430383/8752213

xcp huff_rom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/286532/8761419

tdf scfifo_abq.tdf

--scfifo ADD_RAM_OUTPUT_REGISTER="ON" DEVICE_FAMILY="Cyclone II" LPM_NUMWORDS=4 LPM_SHOWAHEAD="OFF" lpm_width=16 lpm_widthu=2 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EA
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tdf scfifo_ccr.tdf

--scfifo ADD_RAM_OUTPUT_REGISTER="ON" DEVICE_FAMILY="Cyclone II" LPM_NUMWORDS=4 LPM_SHOWAHEAD="OFF" lpm_width=16 lpm_widthu=2 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EA
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htm netopt.htm

Netlab Reference Manual netopt netopt Purpose Optimize the weights in a network model. Synopsis [net, options]
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fpj 默认工程.fpj

[Project] WorkDir=E:\程序库\抗干扰 CompileCmd=C51:SMALL DEBUG OBJECTEXTEND SYMBOLS ROM(LARGE) NOCODE COND AREGS OPTIMIZE(6, SPEED);A51:DEBUG MACRO SYMBOLS MOD51 LIST; Target=8279.omf TargetType=0 MustR
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www.eeworm.com/read/382605/9016664

xcp buffer_img.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enab
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www.eeworm.com/read/382605/9016692

xcp tabla_q.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enab
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