scfifo_abq.tdf

implemention of FPGA and DSP linking port, using Asynchronous mode

--scfifo ADD_RAM_OUTPUT_REGISTER="ON" DEVICE_FAMILY="Cyclone II" LPM_NUMWORDS=4 LPM_SHOWAHEAD="OFF" lpm_width=16 lpm_widthu=2 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" clock data q rdreq usedw wrreq lpm_hint="RAM_BLOCK_TYPE=M4K" RAM_BLOCK_TYPE="M4K"
--VERSION_BEGIN 5.1 cbx_altdpram 2004:12:01:07:29:56:SJ cbx_altsyncram 2005:10:21:05:19:54:SJ cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_fifo_common 2005:07:22:05:40:24:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_compare 2005:07:12:04:41:28:SJ cbx_lpm_counter 2005:08:24:10:49:38:SJ cbx_lpm_decode 2005:04:28:09:28:48:SJ cbx_lpm_mux 2005:04:28:09:25:00:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_scfifo 2005:09:07:08:25:24:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ  VERSION_END


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FUNCTION a_dpfifo_hhq (clock, data[15..0], rreq, sclr, wreq)
RETURNS ( q[15..0], usedw[1..0]);

--synthesis_resources = lut 7 M4K 1 reg 13 
SUBDESIGN scfifo_abq
( 
	clock	:	input;
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdreq	:	input;
	usedw[1..0]	:	output;
	wrreq	:	input;
) 
VARIABLE 
	dpfifo : a_dpfifo_hhq;
	sclr	: NODE;

BEGIN 
	dpfifo.clock = clock;
	dpfifo.data[] = data[];
	dpfifo.rreq = rdreq;
	dpfifo.sclr = sclr;
	dpfifo.wreq = wrreq;
	q[] = dpfifo.q[];
	sclr = GND;
	usedw[] = dpfifo.usedw[];
END;
--VALID FILE