代码搜索：normal
找到约 10,000 项符合「normal」的源代码
代码结果 10,000
www.eeworm.com/read/413863/11139098
control
Source: cdfs-src
Section: misc
Priority: optional
Maintainer: Eduard Bloch
Build-Depends: debhelper (>> 5.0.0), bzip2
Standards-Version: 3.7.2
Package: cdfs-src
Architecture: all
D
www.eeworm.com/read/268231/11148973
m ip_04_05.m
% ip_04_05.m added for spar
a=[-10 -5 -4 -2 0 1 3 5 10];
[y,dist]=mse_dist('normal',a,0.01,0,1)
www.eeworm.com/read/412483/11198291
h iceray.h
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
www.eeworm.com/read/265751/11254674
bat do.bat
set PRODUCTID=CAM_NORMAL
@rm -f b.exe
@rm -f buildHZ.exe
@sh -c "mkdir -p obj"
rem windres -o obj/emfcwinrc.o -i src/win32rc/emfcwin.rc
make PRODUCTID=%PRODUCTID% -f makefile.mingw all 2> a
echo
www.eeworm.com/read/265751/11254697
bat do.bat
set PRODUCTID=CAM_NORMAL
@rm -f f.exe
@rm -f freeHZ.exe
@sh -c "mkdir -p obj"
rem windres -o obj/emfcwinrc.o -i src/win32rc/emfcwin.rc
make PRODUCTID=%PRODUCTID% -f makefile.mingw all 2> a
echo
www.eeworm.com/read/265648/11258718
npl buzz.npl
JDF E
// Created by ISE ver 1.0
PROJECT buzz
DESIGN buzz Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE buzz1.v
MODSTYLE buzz1 Normal
[STRATEGY-LIST]
Normal=True, 1037616
www.eeworm.com/read/265643/11259225
npl clock.npl
JDF E
// Created by ISE ver 1.0
PROJECT clock
DESIGN clock Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE clock.v
MODSTYLE clock Normal
[STRATEGY-LIST]
Normal=True, 10376
www.eeworm.com/read/265642/11259298
npl fosc.npl
JDF E
// Created by ISE ver 1.0
PROJECT fosc
DESIGN fosc Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE fosc.v
MODSTYLE fosc Normal
[STRATEGY-LIST]
Normal=True, 103761567