代码搜索:mult

找到约 6,230 项符合「mult」的源代码

代码结果 6,230
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el mult.el

(progn (load "../g1") (load "../l1") (load "../b1") (load "m1") (load "c1") (load "compressor") (load "components") (setq b 128) (setq w 4) (setq h (gen-tree b w ))
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v mult.v

module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, input enable_in, output reg enable_out ); always @(posedge clock) if(enable_i
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java mult.java

/* * Copyright 1999-2004 The Apache Software Foundation. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * Y
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s mult.s

.globl .m,.q,.r .globl .p,sprv .m: jsr pc,sprv mov (sp),r0 mpy 4(sp),r0 mov r1,4(sp) br 1f .q: jsr pc,sprv mov 4(sp),r1 sxt r0 dvd (sp),r0 mov r0,4(sp) br 1f .r: jsr pc,sprv mov 4(sp),
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plg mult_if.plg

@P: Worst Slack : NA
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msg mult_if.msg

@TM:1137139359 @N: :"":0:0:0:-1|Only System clock will be Autoconstrained @N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report
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vhd mult.vhd

-- MULTIPLEXER TO CHOOSE BETWEEN CLOCK AND C0 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity mul
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vhd mult.vhd

-- MULTIPLEXER TO CHOOSE BETWEEN CLOCK AND C0 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use work.butter_lib.all ; use ieee.std_logic_unsigned.all ; entity mul
www.eeworm.com/read/358243/2992112

java mult.java

/* * Copyright 1999-2004 The Apache Software Foundation. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * Y
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mult_rules

$description = "\ The following test creates a makefile to test the presence of multiple rules for one target. One file can be the target of several rules if at most one rule has commands; the other