代码搜索：modelSim

找到约 1,834 项符合「modelSim」的源代码

代码结果 1,834
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/359174/10163139

versim_par vsp2232.versim_par

VSP2232.versim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (Verilog)
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www.eeworm.com/read/359174/10163263

versim_par top.versim_par

top.versim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (Verilog)
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www.eeworm.com/read/162348/10312232

transcript

# Reading D:/Modeltech_6.0d/tcl/vsim/pref.tcl # // ModelSim SE 6.0d Apr 25 2005 # // # // Copyright Mentor Graphics Corporation 2005 # // All Rights Reserved. # // # // THIS WO
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www.eeworm.com/read/279788/10393598

mti scrambler.cr.mti

E:/testf/scrambler/scrambler.v {1 {vlog -work work E:/testf/scrambler/scrambler.v Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005 -- Compiling module scrambler Top level modul
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www.eeworm.com/read/353393/10450891

txt readme.txt

Disclaimer of Warranty: ----------------------- This software code and all associated documentation, comments or other information (collectively "Software") is provided "AS IS" without warranty
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www.eeworm.com/read/277836/10602044

gfl pn.gfl

# XST (Creating Lso File) : pn.lso # xst flow : RunXST pn.syr pn.prj pn.sprj pn.ana pn.stx pn.cmd_log # XST (Creating Lso File) : pn.lso # xst flow : RunXST pn.syr pn.prj pn.sprj pn.a
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www.eeworm.com/read/277836/10602148

vhdsim_par pn.vhdsim_par

pn.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)
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www.eeworm.com/read/274663/10860244

vhdsim_par xccpld.vhdsim_par

xccpld.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: ModelSim SE (VHDL)
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www.eeworm.com/read/416456/11024521

txt 说明.txt

CAGenerator.vdh为CA编码的vhdl源文件，CAGeneratorTest.do为相应的Modelsim仿真用宏文件 CLKIN为输入的10.23MHz的时钟 X1IN为输入的X1历元信号，用以复位电路 SWITCH为选择卫星号的信号 CAOUT为对应卫星产生的C/A码 CLK50为向数据产生器发送的50Hz时钟信号
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www.eeworm.com/read/469279/6979975

transcript

# Reading E:/altera/72/modelsim_ae/tcl/vsim/pref.tcl # OpenFile "C:/Documents and Settings/chengle/Lb/QuartusII/VHDL/VHDL/my_eda(10)/m/m.vhd"
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