代码搜索：modelSim

找到约 1,834 项符合「modelSim」的源代码

代码结果 1,834
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/17754/756073

xrf item_new2_modelsim.xrf

vendor_name = ModelSim source_file = 1, C:/Documents and Settings/Administrator/桌面/新建文件夹/item_new2.vhd source_file = 1, C:/Documents and Settings/Administrator/桌面/新建文件夹/itemnew3_2.vhd design_name =
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www.eeworm.com/read/17888/765403

pdf modelsim_ tb_spi().pdf

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www.eeworm.com/read/40514/1140228

pdf modelsim_cmd_ref_ug.pdf

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www.eeworm.com/read/213130/4929686

xrf i2c_modelsim.xrf

vendor_name = ModelSim source_file = 1, D:/newwork/i2c_p/soc/i2c.vhd source_file = 1, D:/newwork/i2c_p/soc/i2c_control.vhd source_file = 1, D:/newwork/i2c_p/soc/shift.vhd source_file = 1, D:/newwo
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www.eeworm.com/read/326943/3465612

xrf i2c_modelsim.xrf

vendor_name = ModelSim source_file = 1, D:/newwork/i2c_p/soc/i2c.vhd source_file = 1, D:/newwork/i2c_p/soc/i2c_control.vhd source_file = 1, D:/newwork/i2c_p/soc/shift.vhd source_file = 1, D:/newwo
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www.eeworm.com/read/301574/3837636

xrf i2c_modelsim.xrf

vendor_name = ModelSim source_file = 1, D:/newwork/i2c_p/soc/i2c.vhd source_file = 1, D:/newwork/i2c_p/soc/i2c_control.vhd source_file = 1, D:/newwork/i2c_p/soc/shift.vhd source_file = 1, D:/newwo
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www.eeworm.com/read/285694/4047542

xrf i2c_modelsim.xrf

vendor_name = ModelSim source_file = 1, D:/newwork/i2c_p/soc/i2c.vhd source_file = 1, D:/newwork/i2c_p/soc/i2c_control.vhd source_file = 1, D:/newwork/i2c_p/soc/shift.vhd source_file = 1, D:/newwo
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www.eeworm.com/read/269202/4247025

xrf ad7865test_modelsim.xrf

vendor_name = ModelSim source_file = 1, F:/my_quartus/swt/AD7865test/cnt_500.v source_file = 1, F:/my_quartus/swt/AD7865test/AD7865test.bdf source_file = 1, F:/my_quartus/swt/AD7865test/AD7865.v s
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www.eeworm.com/read/268985/11112390

xrf clk_div5_modelsim.xrf

vendor_name = ModelSim source_file = 1, D:/fpga例子/clk_div5/clk_div5.vhd source_file = 1, D:/fpga例子/clk_div5/clk_div5.vwf design_name = clk_div5 instance = comp, \clk~I\, clk, clk_div5, 1 instance
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www.eeworm.com/read/235739/14054570

vhd xlcosim_dac_test_modelsim.vhd

library IEEE; use IEEE.std_logic_1164.all; entity xlcosim_dac_test_modelsim is port ( dac_test_black_box_din: in std_logic_vector(17 downto 0); dac_test_black_box_fltsel: in std_lo
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